this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.0 2 / jun. 2000 hyundai semiconductor hy 62u 8200 b series 256kx8bit cmos sram description the hy62u8200 b is a high speed , low power and 2m bit cmos sram organized as 262,144 words by 8bit. the hy62u8200 b uses high performance cmos process technology and designed for high speed low power circuit technology. it is particular l y well suited for used in high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0v. features fully static operation and tri-state output ttl compatible inputs and outputs battery backup( ll-part ) - . 2.0v(min) data retention standard pin configuration - . 32- stsopi-8x13.4, 32- tsopi -8x20 (standard and reversed) product voltage speed operation standby temperature no. (v) ( ns) current / icc ( ma) current( ua) ( c) hy62u8200 b 2.7~3.3 70* /85/100 5 25 0~70 hy62u8200 b - e 2.7~3.3 70 * /85/100 5 25 - 25 ~85(e) hy62u8200 b -i 2.7~3.3 70 */ 85/100 5 25 -40~85( i ) note 1. blank : commercial, e : extended , i : industrial 2. current value is max. 3. * measured with 30pf test load pin connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /oe a10 dq8 dq7 dq6 dq5 dq4 vss dq3 dq2 dq1 a0 a1 a2 a3 a11 a9 a8 a13 /we cs2 a15 vcc a17 a16 a14 a12 a7 a6 a5 a4 /cs1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 a3 a2 a0 dq1 dq2 dq3 vss dq4 dq5 dq6 dq7 dq8 /cs1 a10 /oe a4 a5 a6 a7 a12 a14 a16 a17 vcc a15 cs2 /we a13 a8 a9 a11 a1 stsopi/ tsopi stsopi/ tsopi (standard) (reversed) pin description block diagram pin name pin function /cs1 chip select 1 cs2 chip select 2 /we write enable /oe output enable a0 ~ a17 address input i/o1 ~ i/o8 data input/output vcc power( 2.7 v ~3.3v ) vss ground memory array 256k x 8 row decoder sense amp write driver data i/o buffer i/o1 i/o8 columndecoder control logic add input buffer a0 a17 /cs1 /cs2 /we /oe
hy62 u 8200 b series rev.0 2 / jun. 2000 2 ordering information part no. speed power temp. package hy62u8200 b llt1 70*/85/100 ll-part tsopi(standard) hy62u8200 b llr1 70*/85/100 ll-part tsopi(reversed) hy62u8200 b llst 70*/85/100 ll-part small er tsopi(standard) hy62u8200 b llsr 70*/85/100 ll-part small er tsopi(reversed) hy62u8200 b llt1- e 70*/85/100 ll-part e tsopi(standard) hy62u8200 b llr1- e 70*/85/100 ll-part e tsopi(reversed) hy62u8200 b llst- e 70*/85/100 ll-part e small er tsopi(standard) hy62u8200 b llsr- e 70*/85/100 ll-part e small er tsopi(reversed) hy62u8200 b llt1-i 70*/85/100 ll-part i tsopi(standard) hy62u8200 b llr1-i 70*/85/100 ll-part i tsopi(reversed) hy62u8200 b llst-i 70*/85/100 ll-part i small er tsopi(standard) hy62u8200 b llsr-i 70*/85/100 ll-part i small er tsopi(reversed) note 1. blank : commercial, e : extended, i : industrial 2. * measured with 30pf test load. absolute maximum rating (1) symbol parameter rating unit remark v in, v out voltage on any pin relative to vss -0.2 to 3.9 v v cc voltage on vcc supply relative to vss -0.2 to 4.0 v t a operating temperature 0 to 70 c hy62u8200 b - 25 to 85 c hy62u8200 b-e -40 to 85 c hy62u8200 b-i t stg storage temperature -55 to 150 c p d power dissipation 1.0 w i out data output current 50 ma t solder lead soldering temperature & time 260 5 c sec note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. truth table /cs 1 cs 2 /we /oe mode i/o power h x x x des elected hi gh -z standby x l x x des elected hi gh -z standby l h h h output disabled high-z active l h h l read dout active l h l x write d in active note : 1. h=v ih , l=v il , x=don't care ( v ih or v il )
hy62 u 8200 b series rev.0 2 / jun. 2000 3 rec ommended dc operating condition symbol parameter min. typ. max. unit vcc supply voltage 2.7 3.0 3.3 v vss ground 0 0 0 v v ih input high 2.2 - vcc+0.2 v voltage v il input low voltage -0.2 (1) - 0.4 v note 1. v il = -1.5v for pulse width less than 30ns dc electrical characteristics vcc= 2.7v~3.3v , t a = 0 c to 70 c/ -25 c to 85 c (e)/ -40 c to 85 c ( i ) , unless otherwise specified sym . parameter test condition min. typ. max. unit i li input leakage current vss < v in < vcc -1 - 1 ua i lo output leakage current vss < v out < vcc, /cs1 = v ih or cs2 = v il or / oe = v ih or /we = v il -1 - 1 ua icc operating power supply current /cs1 = v il , cs2 = v ih, v in = v ih or v il, i i/o = 0ma - - 5 ma i cc1 average operating min duty cycle = 100% , 70ns - - 60 ma current /cs1 = v il cs2 = v ih 85ns - - 50 ma v in = v ih or v il 100ns - - 50 ma cycle time = 1us, i i/o = 0 ma, /cs1 ?a 0.2v, cs2 ?? vcc - 0.2v v in ?a 0.2v or v in ?? vcc ? 0.2v - - 6 ma i sb ttl standby current (ttl input) /cs1 = v ih or cs2 = v il - - - 0. 5 ma i sb1 standby hy62v8200b /cs1 > vcc - 0.2v , cs2 > 0.2v or - - 25 ua current hy62v8200b-e cs 2 > vcc - 0.2v - - 25 ua (cmos input) hy62v8200b-i - - 25 ua v ol output low voltage i ol = 2.1ma - - 0.4 v v oh output high voltage i oh = -1ma 2.2 - - v note : typical values are at vcc = 3.0v , t a = 25 c capacitance (temp = 25 c, f= 1.0mhz) symbol parameter condition max. unit c in input capacitance v in = 0v 8 pf c out output capacitance v i/o = 0v 10 pf note : these parameters are sampled and not 100% tested
hy62 u 8200 b series rev.0 2 / jun. 2000 4 ac characteristics vcc= 2.7v~3.3v, t a = 0 c to 70 c/ -25 c to 85 c(e)/ -40 c to 85 c( i ) , unless otherwise specified -70 -85 -10 min. max. min. max. min. max. 1 trc read cycle time 70 - 85 - 100 - ns 2 taa address access time - 70 - 85 - 100 ns 3 tacs chip select access time - 70 - 85 - 100 ns 4 toe output enable to output valid - 40 - 45 - 50 ns 5 tclz chip select to output in low z 10 - 10 - 10 - ns 6 tolz output enable to output in low z 5 - 5 - 5 - ns 7 tchz chip deselection to output in high z 0 20 0 25 0 30 ns 8 tohz out disable to output in high z 0 20 0 25 0 30 ns 9 toh output hold from address change 15 - 15 - 15 - ns 10 twc write cycle time 70 - 85 - 100 - ns 11 tcw chip selection to end of write 60 - 70 - 80 - ns 12 taw address valid to end of write 60 - 70 - 80 - ns 13 tas address set-up time 0 - 0 - 0 - ns 14 twp write pulse width 50 - 60 - 70 - ns 15 twr write recovery time 0 - 0 - 0 - ns 16 twhz write to output in high z 0 2 0 0 25 0 30 ns 17 tdw data to write time overlap 3 5 - 35 - 40 - ns 18 tdh data hold from write time 0 - 0 - 0 - ns 19 tow output active from end of write 5 - 5 - 5 - ns ac test conditions t a = 0 c to 70 c / -25 c to 85 c (e)/ -40 c to 85 c ( i ) , unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rise and fall time 5ns input and output timing reference level 1.5v cl = 100pf + 1ttl load output load cl* = 30pf + 1ttl load note * : test load is 30pf for 70ns device. ac test loads cl(1) ttl note : 1 including jig and scope capacitance read cycle symbol # parameter unit write cycle
hy62 u 8200 b series rev.0 2 / jun. 2000 5 timing diagram read cycle 1 (note1 ,4) data valid high-z addr data out trc / cs1 cs2 / oe taa tacs toe tclz (3) t olz (3) toh t chz (3) tohz (3) read cycle 2 (note 1,2,4) trc taa data valid previous data toh toh addr data out read cycle 3 (note 1,2,4) /cs1 tacs data valid tclz ( 3 ) tchz ( 3 ) data out cs2 notes: 1. read cycle occurs whenever a high on the /we and /oe is low /cs 1 and cs2 are in active status. 2. /oe = v il 3. transition is measured ?? 200mv from steady state voltage. this parameter is sampled and not 100% tested. 4. / c s 1 in high for the standby, low for active c s 2 in low for the standby, high for active
hy62 u 8200 b series rev.0 2 / jun. 2000 6 write cycle 1 (1,4,5,9) (/we controlled) write cycle 1 (1,4,5,9) (/ cs1, cs2 controlled) data valid addr data out / cs1 cs2 / we twc tcw twr (2) taw twp data in high-z tas twhz (3,8) tdw tdh tow (6) (7) data valid addr data out / cs1 cs2 / we twc tcw twr (2) taw twp data in tdw tdh high-z high-z tas
hy62 u 8200 b series rev.0 2 / jun. 2000 7 notes(write cycle): 1. a write occurs during the overlap of a low /cs1, cs2 and low /we. a write begins at the latest transition among /cs1 going now, cs2 going high and /we going low: a write ends at the earliest transition among /cs1 going high, cs2 low and /we going high. twp is measured from the beginning of write to the end of write. . 2. tcw is measured from the later of /cs1 going low or cs2 going high to the end of write . 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. twr1 is applied in case a write ends as /cs1, or /we going high, and twr2 is applied in case a write ends at cs2 going low. 5. if /oe, cs2 and /we are in the read mode during this period, and the i/o pins are in the output low-z state, input of opposite phase of the output must not be applied because bus contention can occur. 6. if /cs1 goes low simultaneously with /we going low, the outputs remain in high impedance state. 7. dout is the read data of the new address. 8. when /cs1 is low and cs2 is high, i/o pins are in the output state. the input signals in the opposite phase leading to the outputs should not be applied.
hy62 u 8200 b series rev.0 2 / jun. 2000 8 data retention electric characteristic t a = 0 c to 70 c / -25 c to 85 c (e)/ -40 c to 85 c ( i ) symbol parameter test condition min. typ. max. unit v dr vcc for data retention /cs1 > vcc-0.2v, cs2 < 0.2v or 2.0 - - v > vcc ? 0.2v, vss < v in < vcc i ccdr data hy62u8200 b vcc=3.0v, /cs1 > vcc - 0.2v, - - 25 ua retention hy62u8200 b - e cs2 < 0.2v or > vcc ? 0.2v, - - 25 ua current hy62u8200 b -i vss < v in < vcc - - 25 ua tcdr chip deselect to data retention time see data retention timing diagram 0 - - ns tr operating recovery time 5 - - m s notes: 1. typical values are under the condition of t a = 25 c. data retention timing diagram 1 cs1 vdr cs1>vcc-0.2v tcdr tr vss vcc 2.7v 2.2v data retention mode data retention timing diagram 2 0.4v vdr tcdr tr vss vcc cs2 2.7v data retention mode cs2<0.2v
hy62 u 8200 b series rev.0 2 / jun. 2000 9 package information 32pin 8x20mm thin small outline package standard(t1) unit : inch(mm) 0.319(8.103) 0.311(7.900) 0.728(18.491) 0.720(18.288) 0.792(20.117) 0.784(19.914) 0.025(0.64) 0.021(0.54) 0.008(0.21) 0.004(0.10) 0.020(0.50) bsc 0.011(0.27) 0.041(1.05) 0.037(0.95) 0.006(0.15) 0.002(0.05) #1 #32 #16 #17 0.007(0.17) 32pin 8x20mm thin small outline package reversed(r1) unit : inch(mm) 0.319(8.103) 0.311(7.900) 0.728(18.491) 0.720(18.288) 0.792(20.117) 0.784(19.914) 0.025(0.64) 0.021(0.54) 0.008(0.21) 0.004(0.1) 0.020(0.50) bsc 0.007(0.17) 0.041(1.05) 0.037(0.95) 0.006(0.15) 0.002(0.05) #16 #17 #1 #32 0.011(0.27)
hy62 u 8200 b series rev.0 2 / jun. 2000 10 32pin 8x13.4mm smaller thin small outline package standard(st) unit : inch(mm) 0.319(8.1) 0.311(7.9) 0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2) 0.024(0.6) 0.016(0.4) 0.008(0.2) 0.004(0.1) 0.020(0.50) 0.007(0.17) 0.041(1.05) 0.037(0.95) 0.008(0.20) 0.002(0.05) #1 #32 #16 #17 0.011(0.27) 32pin 8x13.4mm smaller thin small outline package reversed(sr) unit : inch(mm) 0.319(8.1) 0.311(7.9) 0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2) 0.024(0.6) 0.016(0.4) 0.008(0.2) 0.004(0.1) 0.020(0.50) 0.007(0.17) 0.041(1.05) 0.037(0.95) 0.008(0.20) 0.002(0.05) #16 #17 #1 #32 0.011(0.27)
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